Conventional static timing analysis (STA) has been a stock analysis algorithm for the design of digital circuits over the last thirty years. However, in recent years, the increased variation in semiconductor devices and interconnect has introduced a number of issues that cannot be handled by traditional (deterministic) STA. This has led to considerable research into statistical static timing analysis, which replaces the normal deterministic timing of gates and interconnects with probability distributions, and gives a distribution of possible circuit outcomes rather than a single outcome.
In statistical static timing analysis (SSTA), timing quantities are propagated as statistical distributions where traditional deterministic STA timing propagates only single valued deterministic data. The propagated timing quantities include arrival times (AT), required arrival times (RAT), and slews, along with other timing related quantities such as guard times, adjusts, asserts, etc. SSTA and STA operate on a timing graph comprised of points at which signal transitions can occur, which may be referred to as timing points or nodes, and edges that connect incident nodes. Timing values are computed for the timing graph at each node based upon arrival times (ATs), which define the time (or time distribution) at which a given signal arrives at a timing point, and required arrival times (RATs), which define the time (or time distribution) at which the signal is required to get to the timing point, in order to meet the timing requirements. These ATs and RATs are used to compute slacks at nodes (RAT minus AT for late mode and AT minus RAT for early mode). A negative slack for either a late mode test slack or an early mode slack indicates a timing constraint violation.
Each STA timing run considers a single corner of a process space, which represents a set of input values for parameters that may include temperature of the circuit, input voltage, and various manufacturing parameters of an integrated circuit. In order to evaluate the impact that a given parameter will have on timing, multiple STA timing runs must be executed with parameters that affect timing set at several maximum and minimum corners, such as high and low temperature, high and low voltages, and various processing conditions. For example, STA timing runs may compare a corner having high input voltage, low operating temperature, and the best manufacturing parameters with a corner with a low input voltage, high operating temperature, and the worst manufacturing parameters. As a check of the performance of the integrated circuit design, many or all of the corners may be run and the integrated circuit design adjusted until all of the corners pass the timing tests. These results reflect the extreme performance bounds of the integrated circuit and require multiple timing runs.
A significant benefit of SSTA is that, because the timing quantities are propagated as statistical distributions, SSTA provides coverage over the entire process space. For example, a single SSTA timing run may suffice in instances where multiple STA timing runs would traditionally be required. Additionally, a test that passes in a single corner under STA may actually fail in one or more other corners, which would not be discovered unless multiple STA timing runs are performed. Therefore, multiple STA runs would be required to close timing, and even then it may be highly unlikely that the full process space would be covered, as this would be prohibitively expensive. For example, if there were only two corners per parameter, then 2N corners would have to be analyzed by STA timing runs to achieve the same full coverage of the process space boundary provided by a single SSTA timing run.
Statistical methods may also provide intrinsic means of pessimism reduction as a result of the statistical techniques inherent in the method. For example, the propagation of a known independently random term allows for the RSSing of random data between each propagation state. RSSing is taking the square root of the sum of the squares of two quantities, in place of straight summation, resulting in a significantly reduced final product as compared to summation. This technique may be used to account for the conditional probabilities between the data being processed as it would be very unlikely that two uncorrelated variables would both simultaneously occupy their worst case locations. Other pessimism relief may occur when sampling the final distributions, as additional RSSing may occur between terms during projection from a distribution to some example sample value.
Finally, information regarding the probability of particular failure modes may be obtained in SSTA, as opposed to STA, which is binary indicating only a pass/fail condition. SSTA may allow for very low probability fails to be ignored while also allowing for a more aggressive clipping of the statistical tails when used with at speed test. Peripherally, the SSTA results may provide indicators of how the design and/or process may be improved or made more robust by indicating individual sensitivities to the various sources of variation, allowing for more robust designs and improved yields. The result is that SSTA methods can reduce pessimism, effectively improving the performance of any technology node, and this benefit only increases as technology marches forward and variability increases. Additionally SSTA may simultaneously provide a means to tune processes and designs for increase robustness and yield.
Benefits of SSTA, however, do come with associated costs, and mitigation of these costs goes a long way towards making SSTA a practical approach. One of the more significant costs is related to a significant increase in memory requirements. In every location where STA would store a single timing value (e.g., an arrival time), SSTA must store a complete statistical description of the same timing quantity. The statistical description may contain at least N+3 terms, where N is the number of sources of variation and the additional terms include a distribution mean, an independently random term, and a term for systematic variation. Currently the number of sources of variation may exceed ten, and this will likely grow with advances in technology. Also, the number of sources of variation can increase appreciably when spatial variation is considered, as in the case where the effects of all surrounding topology is also considered at a given timing point. Therefore, the memory required to store a single timing quantity in SSTA may often be a factor of ten times or more than the memory required in STA. This memory requirement may pose a significant obstacle to SSTA analysis as contemporary STA is already pushing the storage limits of typical available memory for large designs.
What is needed therefore is a method to implement SSTA for timing analysis that overcomes the need for large memory requirements and other deficiencies of conventional approaches to SSTA.